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L6256 12v combo description the 12 volt combo chip is a combination spindle motor driver, voice coil driver and d/a converter. the part can be used in,application like hdd. the vcm amplifiers drive a low impedance coil and are set up to accept rc compensation, which allows a wide bandwidth with absolute minimum phase lag. the sense resistor/amplifier arrange- ment allows full current loop operation. the loop gain is changeable by attenuating the vcm dac voltage amplitude in cascadable stages. the spindle driver is a pwm only voltage loop with power supply feedforward, driving a 3 phase sensorless brushless dc motor. since it uses pwm operation at full run speed, it has output slew rate control during start and run modes. there is an inductive clamp circuit to limit flyback voltage transients across the supply voltage dur- ing motor phase changes and during the braking sequence. only the 2 phase or bipolar commuta- tion pattern is produced by the internal commuta- tion circuitry. a commutation register allows arbi- trary winding sequencing during certain opera- tions. internal protection against crossover spikes is built in. 3 phase or tripolar commutation can be supported in software during start by writing a commutation pattern directly to the preload register. tripolar operation requires that more than two phase drivers contribute current simultaneously. the current limit circuitry reflects this and allows 33% higher current limit, which produces nearly december 1997 charge pump vpwr 2 uv detect por vcm command channel 10 bit dac vcm retract vcm control clk sync serial interface bandgap voltage reference current sources spindle logic spindle sequencer analog test mux 3 24 3.3v linear regulator 3 feedforward compensation vcm logic thermal h_vpwr h_vpwr + - a amp + - b amp a_out b_out brake delay counter bemf sensing zero crossing detection pwr gnd vcm class ab drivers r_ slew pwm_ in pwm_ dc ff_ comp sp_ clk upper lower pre-drivers dynamic clamping spindle drivers current limit sensing sh_ out bemf_ det sp_ g2 sp_ g1 ref_ in c_tap sp_c sp_b sp_a sp_p2 sp_p1 vc_pwr a_in i_vc io_vc dac cp_out cp_cap h_vpwr vdd vcc npor por_rc park sclk sdio cselb bypassc qdrive vreg_in cur_in 6,7,17,29,39,40 8 11 36 37 5 38 12 35 44 4 41 3 1 43 42 2 24 23 25 30 26 31 32 18 19 33 34 15 10 9 27 13 14 28 16 20 21 22 d97in571 sync clamp figure 1. block diagram plcc44 ordering number: L6256 1/28
constant torque. this is a very high power dissi- pation mode, meant only for momentary opera- tion in unusual circumstances. spindown during a power failure uses the back emf voltage generated by the spindle motor to provide power to the vcm amplifier. the spindle motor coasts during the brake delay time to allow time to park the head actuator. the park circuit is a constant voltage circuit settable externally. after the head is parked, braking commences. the brake operates by shorting all 3 windings. the spindle output stages stay on as long as is required to bring the motor to a complete stop, even if no power is applied to the part. a power on reset (por) function provides pulse stretching for the bidirectional por\ bus, to en- sure that the processor and clocks are at running speed before allowing them to function. 5 volt and 12 volt pins are used directly for the un- dervoltage detect circuit. this allows direct use internally of both supplies. voltage monitor margining is supported. an external 3.3v linear regulator is provided and tied into the por circuit. absolute maximum ratings symbol parameter value unit v pwr normal operating voltage 15 v v pvr inductive clamp voltage @ 2mh, 1.6a, 3% duty cycle <20 v (1) v dd 15 v v cc 6.4 v i_vcm, aout -2 to v pwr +2v logic i/o, sh_out, pwm_dc -0.3 to v cc +0.3 all other pins -0.3 to v pwr +0.3v t stg storage ambient temperature -65 to +150 c esd capability 2kv (1) limited by chip clamp voltage. 1 2 3 5 64 7 8 9 10 12 11 13 14 15 16 17 39 38 37 36 34 35 33 32 31 30 29 40 41 42 44 43 23 22 21 19 18 20 28 27 26 24 25 sp_b sp_p1 sp_c sp_clk gnd sp_g1 gnd c_tap sp_p2 sp_g2 sp_a gnd r_slew por_rc npor bemf_det pwm_in sclk sdio vcc bypassc 5v_gnd gnd sh_out ff_comp pwm_dc vdd ref_in h_vpwr dac io_vc a_in gnd b_out cur_in vreg_in cp_cap cp_out qdrive cselb park i_vc vc_pwr a_out d97in572 pin connection operating conditions v cc = 4.5 to 5.5v v dd = 10.8 to 13.2v 0c < t amb < 70c. description (continued) L6256 2/28
thermal data symbol description value unit r th j-pins r th j-amb thermal resistance junction-pins thermal resistance junction-ambient (*) max. max. 12 50 c/w c/w (*) mounted on board with minimized dissipating copper area. pin description pin # pin name pin description type 1 sp_b spindle output, ph b power/output 2, 42 sp_p1, sp_p2 spindle driver supply power/input 3 sp_c spindle output, ph c power/output 4,44 sp_g1,sp_g2 spindle driver ground power/output 5 sp_clk spindle clock input cmos/input 6,7,29,39,40 gnd power ground ground/heatsink 8 r_slew spindle slew/feedfwd osc. freq. analog/input 9 por_rc ext. por timing cap. analog/output 10 npor por reset (active low) cmos/bio 11 pwm_in spindle pwm input cmos/input 12 bemf_det spindle bemf output cmos/output 13 sclk serial data clock cmos/input 14 sdio bidirectional serial data i/o cmos/bio 15 vcc 5v digital supply supply/input 16 bypassc not to be used - 17 5v_gnd 5v supply ground ground/output 18 cp_out charge pump pumping cap analog/output 19 cp_cap charge reservoir cap analog/input 20 qdrive 3.3v regulator base drive analog/output 21 vreg_in 3.3v regulator voltage feedback analog/io 22 cur_in 3.3v regulator current feedback analog/io 23 b_out vcm driver output, b power/output 24 vc_pwr vcm drivers supply power/input 25 a_out vcm driver output, a power/output 26 i_vc vcm sense amplifier input analog/input 27 park vcm park pin analog/input 28 cselb chip select - 30 a_in vcm a-amplifier input analog/input 31 io_vc vcm sense amplifier output analog/output 32 dac vcm dac command output analog/output 33 h_vpwr vcm vpwr/2 reference voltage analog/output 34 vdd 12v analog supply supply/input 35 ref_in spindle current limit/win threshd analog/input 36 pwm_dc spindle filtered pwm input analog/input 37 ff_comp spindle feedforwd ramp generator analog/input 38 sh_out spindle bemf sample/hold analog/output 41 c_tap spindle centre tap analog/input 43 sp_a spindle output, ph a power/output L6256 3/28
6,7,29,39,40 gnd r slew 100k ? por_rc c2 47nf bemf_det 12 9 8 sclk 13 npor 10 v + - v cc 14 sdio rdio 1.2k ? 15 vcc 20 qdrive r s 1.5 ? 21 vreg_in 22 cur_in c3 22 f esr 0.5 ? 17 5v_gnd vc_pwr 35 ref_in r ref 62.5k ? r ref2 120k ? 18 cp_out 19 24 cp_cap r_slew r pwm 33k ? 11 pwm_in bypassc cbyp 10nf 16 v + - v dd 4 sp_g1 44 sp_g2 c pout 33nf d4 d5 c pcap 2.2 f 35v d1 34 vdd c1 4.7 f 25v 41 43 1 3 sp_c sp_b sp_a c_tap 42 sp_p2 c hvpwr 100nf 33 h_vpwr 32 dac r b 4.3k ? 31 io_vc r a 1.5k ? 30 a_in 27 25 park a_out r p1 51k ? r p2 100k ? c fb 390pf r fb 120k ? r sense 0.75 ? 26 i_vc 23 b_out 2 sp_p1 spindle c ffc 470pf 37 ff_comp 38 c sh 3.3nf r sh 100k ? sh_out 36 c dc 10nf r pwindc 100k ? pwm_dc 5 sp_clk 28 cselb pwm npor d97in573 vcm sp_clk sp_c sp_b sp_a c_tap i_vc b_out bemf_det sclk sdio vpwr 3.3v cselb (from p) typical application diagram design formulas: 1. spindle run mode slew rate: sr = 1500 ? 10 3 rslew ( volts / s ) 2. feedforward compensation: fpwm = 1 tpwm = 1 cffc ? rslew ( hz ) dout = tpwm tpwm + 0.7 s ? vref vrslew ? din v ref = rpwmdc rpwm ? 2.47 ( v ) vrslew = ( vpwr + 0.8 ) 1.86 ( v ) fpwm = pwm chopping frequency din = input duty cycle at pwm_in dout = spindle output duty cycle 3. current limit: ilimit = 20 ? 10 3 ? vcc rref ( a ) 4. bemf zero crossing detector: - slope compensation: csh ? rsh = 5.9683 vbemf ? n ( sec ) vbemf = amplitude of bemf n = run mode speed of the motor in rpm - window width: t win = 15404 ? vcc ? rref rref + rref2 ? vbemf ? n ? polepair ( s ) 5. vcm parking voltage: v a,park = 0.5 ? ? ? ? 1 + rp2 rp1 ? ? ? ( v ) 6. 3.3v regulator: max load current: i max = 0.3 rs ( a ) L6256 4/28
general block descriptions (see figure 1) charge pump the charge pump provides bias for the upper driv- ers, for the brake circuit, and for internal circuitry as required for normal and spindown operation. slew rate control is built in for quiet operation. serial interface the serial interface will transfer all control, status and data to and from the processor. internal test- ing provisions have also been made through this port. the interface is compatible with an 8x196mp,nu or k17 series processor at low speed only, due to internal limitations of the proc- essors. external chip select is mandatory on the L6256. chip select is also used to reset and syn- chronize the serial port. the serial port is used to indicate thermal shutdown of the dolphin chip. brake delay timer the brake delay will, upon start of a park or brake sequence, delay 128 negative zero crossings of the a spindle phase to allow the park circuit to op- erate. (the delay will typically be on the order of 400 msecs.) then the braking sequence can be- gin. the output of this timer is provided to the se- rial port registers to indicate the start of the brake action, and to indicate the start and end of the park period. 3.3v regulator the 3.3v external regulator provides a logic 3.3v using an external pass element (n channel fet), tied into the undervoltage detection system. it has the following features: voltage mode control, using no external com- pensation. 3:1 foldback current limit to protect the pass element in case of component failure. absolute regulation of 8% under all operating conditions control registers see serial port section. internal testing this circuitry is per vendor?s specifications. no test functions actuated by the serial port software allow chip or drive damage to inadvertently occur. double level write enabling is used. differing ven- dor test requirements are accomodated using the unique vendor code bits. various external pins are used for this function; consult the manufac- turer?s data sheets. spindle section spindle current limit the spindle current limit value in start mode is set by the value of the external resistor on the ref_in pin during start (which at start is shorted to vcc, and the current out of the pin sets the current limit value). during run, various internal methods are used to set a nominal maximum current value for circuit protection only. consult the data sheets and ap- plication notes for a description of this circuitry. current limit operates on a cycle by cycle basis. the current limit comparator output is provided to the serial port to indicate when the spindle is in current limit. the current limit bit is reset when the status register is read. note: current limit operation involves chaotic states, and careful firmware control can be used, if desired, to prevent audible squels. actual cur- rent limit value is also affected significantly by motor inductance. see application notes. commutation counter (cctr) the commutation counter provides commutation control for the spindle motor. it advances the spindle phases according to the bipolar phase control sequence, every time a spin_clk posi- tive edge is received. its reset state (b c\) is gov- erned by the commutation preload register (cpr). operation of the register is synchronous with sp_clk, but the reset is asynchronous. commutation preload register (cpr) during the initial start period, phase on/off control is preloaded into the counters from the commuta- tion preload register, which is loaded from the serial port. this allows direct commutation con- trol from the processor. various commutation schemes are implemented during startup by soft- ware through this register. high side bits take precedence over low side bits. for both high and low drivers, logic high input to this register turns on the respective driver. any pattern other than all 1?s holds the cctr in reset, and sets the mux to bring data from the cpr register for the drive pattern. an all 1?s pattern (an illegal state) releases the cctr reset and switches the mux to read the cctr. an all 0 pattern in the cpr spindle control bits both tristates the spindle drivers and resets the commutation counter. the commutation latch holds data from either the cpr or the cctr depending on whether all 1?s are loaded into the cpr. the latch loads the pre- vious state of the counter when the sp_clk edge comes in. the latch circuitry also provides chop commutation information. L6256 5/28
upper and lower spindle drivers the spindle drivers provide commutation switches. internal inductive flyback protection is provided, dumping the energy into vpwr node. this protection network also provides the energy transfer to the vcm to allow parking after power is lost. the high/low and low/high slew rate of the drivers during run mode is controlled by the r_slew pin to ensure that cross conduction with the lower drivers does not occur, and that excessive volt- age slew rates are not produced. provisions are made to drive inductive loads due to the possible filtering requirements. windings must be damped with suitable external resistors to allow back emf to be detected through the chopping waveform. inductive clamp circuit the inductive clamp is applied to the motor pins to prevent the energy from the spindle motor coils from producing excessive voltages on the part, when the spindle drivers are tristated or when commutation occurs. back emf detect the back emf voltage from the spindle motor is monitored by a sample/hold circuit. first order slope compensation, set by the value of rsh and csh on the sh_out pin, is used to reduce jitter. sampling will occur during the spindle pwm on time, and hold during the off time and the on_delay time. slope compensation must be optimized for operation at run speed. during startup, the zero crossings are detected from all three phases. during run, only the falling edge of phase a is useful for timing. a very small amount of hysteresis is provided to prevent noise glitches. a fixed offset of approximately vebias millivolts is internally introduced to the comparator during start mode. the inductive flyback pulse must be masked by the width of the sp_clk pulse provided by the western digital controller chip. the width of this pulse is affected by motor speed and current, as well as inductance. additional back emf conditioning circuitry is be- ing provided by western digital?s digital controller chip. the back emf_det pin is masked for ap- proximately 1/4 of the expected commutation cy- cle, and is latched to prevent multiple transitions. at power on reset, bemf_det is tristated to allow for in circuit testing. during run mode, the ref_in pin sets a prequali- fier comparator voltage level, which enables the zero crossing detection circuit about 20 s ahead of the actual position. once speed has been sta- bilized, the spindle phase advance is used to ad- just the emf crossing to be coherent with the pwm timing. this is done by observing the output of the preqalifier comparator and comparing it with the on_delay signal internal to the chip. this output comparison is provided through the serial port. feedforward compensation (ffwd comp) any vpwr variations are nulled out by the ra- tiometric adjustment of the pwm duty cycle. this circuit converts the fixed processor pwm fre- quency down to a frequency determined by the r_slew resistor and the ff_comp capacitor. this frequency is very constant over the entire specified supply voltage range. vcm section vcm dac the vcm dac buffer brings the vcm_dac out- put up to the required drive capability. a 10 bit monotonic dac is provided for the vcm. attenuator switches these provide variable attenuators for the vcm current control loop, settable from the control reg- ister. attenuation settings are cascadable in bi- nary form, thus requiring 1 bit for each attenuator. ratios of 1.5:1, 2:1 and 4:1 give the additional combinatorial gains of 3:1 (1.5*2), 6:1 (1.5*4), 8:1 (2*4) and 12:1 (all 3 attenuators on simultane- ously). attenuator gain ratios are not precisely controlled relative to one another and differ slightly between manufacturers. an overall attenuator enable bit has been added to the vcm_dac register address field. if this bit is a 1 (combo compatible mode), then the attenu- ators are enabled. if the bit is a 0, then full gain is requested. this enables the vcm_dac write to accomplish a complete gain shift and dac write in a single serial port operation (2 bytes). level shift the level shift circuitry shifts the center voltage of the vcm current command up to approximately half of the supply voltage, to provide for symmet- ric operation of the vcm power amplifiers. the reference voltage output is a high impedance input point of approximately rref ohms to allow for external bypassing. vcm amplifiers the vcm amplifiers are complementary class ab output amplifiers, with bout having higher gain than the aout amplifier. this ensures uniform saturation in either direction. L6256 6/28
saturated seek bit the processor can command the vcm amplifiers to hard saturate, in the polarity determined by the sign bit of the dac. the saturation detector bit is not the echo of this bit, but is a separate compa- rator bit representing the true state of the ampli- fier. thus, it can be used for loopback testing of the dolphin. vcm current sense amplifier the input differential voltage of the amplifier can be limited to low voltage, but common mode re- jection is very high. the amplifier is capable of operating smoothly when the vcm amplifiers are saturated, providing no input charge buildup or other anomalies. charge does not build up on the inputs even when vcm inductance forces the inputs substantially above the supply or below ground. saturation detector this detector notifies the processor when the commanded vcm current does not match the ac- tual vcm current. the threshold is set by vc_sat. fault detection uv detection the power supply undervoltage protection is set up for the appropriate tolerances, and causes a low signal on por\. a small hysteresis is in- cluded on the voltage comparators, and band- width limiting techniques are used. current limit from the 3.3v regulator has been added to the por error inputs. power on reset (see appendix b) the power on reset circuit provides the following functions: a retriggerable one shot of several millisec- onds. an interlock circuit which provides for dis- charge of the one shot, and a clamp to hold the por\ line low during the timing interval. circuitry to pull por\ high quickly after the 1 shot has timed out. a current source or weak pullup to pull the por\ line high against external leakage cur- rents. undervoltage conditions override external inputs and force por\ low. external inputs do not cause pulse stretching; all internal inputs do. pcba in-circuit testing can arbitrarily pull this line low as necessary to restart the system. alter- nately, a 1 milliamp current can be introduced to the timing capacitor to speed up the por timeout. thermal limit the thermal limit of the chip is set for thlimit with thhyst degrees of hysteresis. thermal limit is a relative voltage, above thwarn for tolerance rea- sons, and must protect the part; it indicates that thermal limit is taking place by disabling the serial port (see serial port section). a park and a spin- dle driver tristate is performed when thermal limit occurs. thermal warning thermal warning is made available to the proces- sor as a status bit in every register, to allow a modified control algorithm strategy that reduces power dissipation and drops chip temperature. park circuit the park circuit provides smooth head retraction. in park, the vcm is switched to voltage mode. bout is grounded. the a amplifier?s positive in- put is switched from the normal half supply refer- ence down to vpark , and aout applies the volt- age determined by vpark and rp1 and rp2 . this damps any motion that may been in progress and causes the head to retract into the latch. L6256 7/28
por power up spindle z (defaults) cpr brake start no slew 3ph emf cpr limit cpr start cctr no slew 3ph emf limit brake start* sp_en* cpr* sp_clk cpr=1's* sp_clk por uv sp_clk* sp_en* start* reg brake run slew 1ph emf cctr no limit start* sp_clk sp_en por reg brake uv fault tristate brake delay thermal tristate thshut thwarn uv d97in585 figure 2: spindle state diagram. note: in the spindle state diagram, in transitioning from start mode to brake, the cpr register is shown as being one possible path. the cpr register can be used to command a brake, which then causes the outputs to brake. this is called cpr brake mode. however, a true brake state does not really occur. specifically, current limit is still active. note: start and sp_en bits and cpr is rewritten to get out of spindle z state. sp_en must be pulsed. note: all spindle state transitions require an sp_clk edge. vcm grounded power on vcm active tristate register park vc_en reg park dac (done=1) sp_enb reg brake fault brake delay d97in586 delay vcm_tristate vc_en reg park fault park fault (fault)= por or uv or th_limit figure 3: vcm section state diagram. note: vc_en must be rewritten to get out of vcm grounded state. note: at start, the spindle and vcm can now be simultaneously enabled. this is a very high power dissipation mode. if this is done, be sure to use the sat_sk bit and duty cycle the vcm to keep chip power dissipation at a reasonable level. L6256 8/28
electrical characteristics power on reset section por specifications specification parameter required value vcc max undervoltage detect trip point, vuv 4.06 to 4.3 vcc trip point hysteresis 1% vdd undervoltage detect trip point vuvd 9.3 to 9.8 volts vdd trip point hysteresis 1% max por\ delay timing 100 msecs forcing current to reset por_rc (for in circuit test only) nominal 1 milliamp ac uv detection - nondetectable pulse tuvmin (1) 1 sec ac uv detection - detectable pulse tuvmax (1) 20 secs (1) ac detection test: done on either supply. with either supply at 0.2 volts above the trip point, a 1.2 volt negative pulse is applied. chip must not respond to pulse width of tuvmin, and must respond to tuvmax. symbol parameter test condition min. typ. max. unit v min required v cc or vdd for valid por\@25c (7) 1.3 2.0 v v tcap timing cap timeout threshold 2/3 v cc v v cth timing cap threshold (10) t strech por\ pulse strech width 5 40 100 ms (5) t tol % por\ pulse tolerance 20% (6) t pmin acc external por\ input required pulse width 300 ns (9) v lw voltage measurement point for tpmin 0.8 v i weak pullup current, por\, steady state (at 3v) 100 a t rise rise time on por\, internal driver with 100pf load (2) 100 ns i pullup pullup current, por\, momentary 3.2 ma notes : (1) dvmarg% the margining limit is determined as a fraction of the actual chip margin circuitry. (2) hysteresis on por\ is optional. load: por\ w ill see approximately 90 pf plus an external pullup source of approximately 6k ohms. no external bulk capacitance is used on por\. (3) fall time measured from 2 volts to 0.8 volts. (4) pulse width measured from vporint volts on falling edge to 1.6 volts on rising edge. (5) is capable of meeting this timing with a 0.1 f or less, 20% tolerance ceramic capacitor. nominal design point, .047 f is 40 ms 20%. (6) timing tolerance on por pulse width irrespective of external parts. (7) por\ is valid if either vcc or vdd exceeds this voltage. (8,9) tpmin acc is the minimum por\ pulse width which the combo must recognize as a valid external por. this corresponds to th e width of the reset pulse from the processor. pulse widths narrower than this may or may not be recognized. tpmin rej is the v alue of pulse width above which the combo should not recognize a pulse. (10) v bounce is caused by the transition between the external por circuit and the internal por clamp circuitry. in order to prevent deadly embrace with the microprocessor. the specified value is needed with 3.3v logic circuitry. L6256 9/28
protocol (general): this protocol is part of a multiple chip protocol which affects several different western digital chip specifications. changes to this protocol will affect several vendors. specifications for this chip conform to the timing specification the serial protocol used to communicate with the chip is based on a fixed length 2 byte write or 3 byte read cycle (packets). each packet sent to the chip is qualified by dolphin chi select and by the address section of the first byte sent to the chip (bits transferred on clock cycles 2 through 4). the r/w bit determines packet length and bus di- rection. at the end of the 16th bit (write) the data is trans- ferred to the appropriate registers. at the end of the 8th (read) bit, the internally ad- dressed registers is ready to be placed on the se- rial bus. a dead bit is provided in all cases as the first bit read back from the dolphin, to allow inter- nal propagation delays and to provide for use of the clock to gate data into the internal shift regis- ter. at high data rates the processor has to insert some time in order to turn the bus around from write to read mode. multiple packets can be sent back to back without a dead space in between when other chips are addressed (except for the specified clock cycles inserted by the processor hardware). the chip is able to decode this case. at high data rates, a dead space of at least 1 clock cycle must be allowed in between bytes of the packet for propagation delays internally. t fall v cc v min v tcap por\ v ccmin v tcap v cth internal por t pmin t stretch v min v min v lw v porint d97in587 figure 4: power on reset waveforms and timing thermal shutdown section symbol parameter value unit t hlimit thermal shutdown die temperature (1) 15 5 above thwarn c t hhyst thermal shutdown hysteresis (1) 10 c t hwarn thermal warning (1) 145 15 c (1) guaranteed by design serial port section general specification data rate 6 to 12.5mhz clock byte synchronization internal max load to external parts 15pf max external load 5ma or 1.2k pullup max bus load capacitance 60pf output drive structure 3 state, active high and low (not open drain) min speed without dead bit 7mhz (see timing section) (1) internal pullup resistor none (1) clock duty cycle of 40% to 60% L6256 10/28
read and write clock rates may differ by as much as 2:1. clock rates may differ between different chips using the bus. a logic inversion may be used by other chips on the bus. if this is done, use of the chip select line after transmissions to the other chips is manda- tory. chip select the external chip select masks out any incoming data. when inactive, the serial port bit clocking state machine is cleared, providing a resync mechanism. the chip select may not change states between every packet transmission, so it should not be counted on as a continuous signal. if the dolphin is the only chip on the serial port, the chip select will only be used an emergency re- sync if the chip doesn?t answer queries. if an address byte is received that is not ad- dressed to the dolphin while chip select is active, the dolphin will ignore the transmission. a metal option in the chip select circuit will allow for either polarity of active level. present intention is for an active high level on the chip select pin. logic inversion on serial port if a logic inversion is used by other chips on the serial bus, the r/w bit will assume the wrong state and the dolphin state mechanism will lose synchronization. in this situation, it will be manda- tory for the processor to deassert the chip select to mask the serial port data intended for the other chip. typical bus waveforms are shown below, with the resultant activity. sclk sdio cselb a1da2d wrong address 1) block mode write - to other chip (a1 and a2 ignored) 2) valid writes to L6256 sclk sdio cselb a1 d a2 d b (all data written) d97in588 figure 5. serial port chip select operation. L6256 11/28
figure 6. serial port chip select operation. transfer protocol formats read: 3 bytes dead cycle bit #01234567 clock #12345678 bit r/w- s0 s1 s2 r0 r1 r2 r3 1 cycle min (1) reply: bit d0 (null) d1 d2 d3 d4 d5 d6 d7 bit d8 (null) d9 d10 d11 d12 d13 d14 d15 (1) normally, this dead cycle time is met by the serial port turnaround delay time. format for write to the dolphin dac, 12v combo compatible mode: write: 10 bits to dac dead cycle bit r/w- s0 s1 s2 a0 (1) a1 d8 d9 1 cycle min d0 d1 d2 d3 d4 d5 d6 d7 1 cycle min L6256 12/28
format for write to the dolphin dac: write: 10 bits to dac dead cycle bit r/w- s0 s1 att_enb (*) a0 (1) a1 d8 d9 1 cycle min d0 d1 d2 d3 d4 d5 d6 d7 1 cycle min (*) indicates a change in the specification. if the att_enb is a 1, then the dac output attenuation will be enabled, and the attenuation will be what- ever has been previously written in the vcm control register (this may include no attenuation at all). if the bit is 0, the attenuator is disabled and high gain is forced. format for write to all other dolphin registers: write: 10 bits to dac dead cycle bit r/w- s0 s1 s2 a0 (1) a1 d8 d9 1 cycle min d0 d1 d2 d3 d4 d5 d6 d7 1 cycle min format for write to the chips other than the 12v combo: write: 1byte dead cycle bitr/w-s0s1s2a0a1a2a3none (1) d0 d1 d2 d3 d4 d5 d6 d7 none (1) (1) there may not be a dead cycle between write addresses and their data bits when data is addressed to another chip on the ser ial port. note: all registers are accessible during por to allow for in circuit testing. appropriate functional chip changes may be occ urring during the reset. serial port timing specifications parameter from/to min. typ. max. units t setup v dh or v dl to v ch 45 ns t hold sclk high to invalid sdio, read 0ns t suw valid sdio to sclk high 10 ns t holdw sclk high to invalid sdio, write 5ns t csck cselb low to first falling clock 133 ns (1) t cschigh last rising clock to 133 ns (1) cselb high (1) cselb specifications apply to both read and write operations. timing is only shown in the read operation digram. minimum timing for non-dead bit operation: timing parameter ref point min. typ. max. units t sclklow sclk vdl to vdh 56 ns t sclkhigh sclk vdh to vdl 56 ns threshold voltage for sdio, internal to dolphin: v th sdio logic threshold 1.0 1.2 1.7 v L6256 13/28
table of address values s0, s1, s2 always 1 - any other value indicates a packet for use by another chip. s2 may be used only as part of the vcm register address, as att_en. register a0-3 r/w vcm dac 11xx write only aux control register 0111 r/w vcm control register 0001 r/w commutation preload register (cpr) 0011 write only test register (*) 1000 r/w status register 0100 read only (*) represents revised specification.the test register is now imple- mented in both chips register bit definitions all bits in the control registers are asserted (true) when positive. the appropriate status bit answers to the same address and bit location as the wri- table bit which causes the action. this means that when a read is performed, the actual value read back is not just an echo from the write register, but represents the status of the function requested. in most cases this is a direct, unlatched output from internal circuitry. most status bits are reset after being read once. the control registers have control bits as follows: test conditions for serial port timing spec: parameter from/to min. max. units t r , t f sclk rise, fall 5 ns v dh 2.4 v v dl 0.8 v v ch 2.4 v note: the serial port must meet these specifications up to the thermal shutdown temperature. figure 7. serial port read timing waveforms figure 8. serial port write timing waveforms L6256 14/28
vcm control register address: 0001 bit function mnemonic bit # init state r/w read 1 indicates: vcm dac attenuation switches - 3 bits (5)d 1.5:1 att0 0 xxx w n/a 2:1 att1 1 xxx w n/a 4:1 att2 2 xxx w n/a thermal limit th_lim 3 0 read th limit register park rpark 4 on r/w park delay is occuring (1) saturate seek sat_sk 5 0 r/w driver saturated (2) vcm tristate vcm_3s 6 xxx w tristated (3) vcm loopback (read) done disable (write) (6) vcm_lp done_dis 7 7 xxx read write current outside window (4) (1) register park will not cause a brake to occur. the register park bit will also go low during a register brake, indicating to the firmware that the brake sequence has been initiated. (2) saturated seek bit, when 1, will cause the vcm drivers to saturate, with the polarity of the sign bit in the vcm dac regist er. a read of this bit indicates that the commanded current differs from the actual current (output of the saturation comparator). note: this is not just an echo of the state of the written bit, but actually represents the true status of the vcm current loop. (3) this bit tristates but leaves internal circuitry active for external test (st), or is unused (unitrode). the done_dis bit h as been moved (see note 4). (4) vcm loopback is optional. use the saturated seek bit for test purposes. the done_dis bit is used to end the park timer cycl e, which may be necessary if the chip is ever put into run mode at low speed. (5) exact attenuation ratios may vary slightly between manufacturers. see data sheets. attenuators are now gated by att_en, whi ch is lo- cated in s2 in the address space of the vcm register. ifatt_en is high, the attenuation is set by the value in this register. i f att_en is low, full gain (no attenuation) is selected. this allows rapid switching between low and high gain with the same write packet a s that used to write to the dac. (6) done_dis must be cleared when entering run mode, or the park timer w ill stay off. this bit should never be used except during error recovery. commutation preload register (cpr-write only) address: 0011 bit function bit address spindle abc low enb (3 bits) initial state: xxx (2) a low enb bit 0 b low enb bit 1 c low enb bit 2 spindle abc high enb (3 bits) initial state: xxx (2) a high enb bit 3 b high enb bit 4 c high enb bit 5 spare bit 6 spare bit 7 notes: - all bits become valid only on a rising sp_clk edge, except chb_enb. - spindle high bits override low bits. transition from low to high and vice versa are interlocked against simultaneous enables or momentary shootthrough. - an all 1?s pattern in this register, bits 0 through 5, causes the internal commutation counter to begin operation on the next spin_clk input edge. any other pattern causes the spindle commutation counter to reset (bc\ state). (1) chb_enb, when high (the por and default condition), allows the back emf chop blanking comparator to disable spindle pwm off peri- ods during the a phase negative crossing (see back emf detection section). initial state varies between vendors. (2) the 6 bits which determine the spindle driver must be set to all 1?s before entering run mode or the cctr will not run. L6256 15/28
auxiliary control register address: 0111 bit function mnemonic init state r/w bit # read 1 indicates: start (1) start xxx w 0 n/a vcm enable (2) vc_en 0 w 1 enabled (5) spindle enable (3) sp_en 0 w 2 enabled (5) thermal limit ovtemp 0 r 3 th limit test enable (7) t_en 0 w 4 enabled (5) software por spor off w 5 always 0 (5) spare register brake rbrake disabled (4) r/w 7 braking * (6) notes: (1) start disables slew rate control. it also changes the back emf detection circuitry from 3 phase to single phase. (2) shuts down active circuitry and drives to the ground state when 0. a transition on this bit is required to reactivate the vcm. see state dia- gram. (3) shuts down active circuitry and tristates when 0. a transition on this bit is required to reactivate the spindle circuitry . see state diagram. (4) writing to brake will cause a register park, then a brake sequence (an internal por), without causing an external por\. th us, the rest of the system including the processor will not be reset. (5) optional bits. (6) the register brake function has been redesigned to allow use of a momentary, current limited brake during start mode only. asserting this bit overrides the cctr or cpr register contents without disturbing them, and causes a brake on the spindle outputs. resetting the bit restores the previous state ( the outputs were in before the bit was asserted). do not attempt to change the cctr or cpr, or send a sp_clk while this bit is asserted. (7) test enable is used to enable manufacturer specific test circuitry within the chip. this bit should be initialized with a 0 value and left at 0 at all times. do not attempt to use this bit for any reason unless you have complete manufacturer specific information. test register address: 1000 bit function init state r/w read 1 indicates: bits: tbd up to 16 read, 8 write note: the test register requires 2 level access. that is, the test enable bit in the aux control register must be written to wi th a 1 or the test register is locked out. status register (read only) mnemonic address: 0100 status bit high indicates address dead bit (unusable for timing reasons) - n/a bit 0 uv detect uv_det * undervoltage occuring bit 1 overtemperature warning twarn exceeded warning temp bit 2 overtemperature shutdown ovtemp exceeded shutdown temp (1) bit 3 version number (2 bits) vers * (2) 4 = bit 0 5 =bit 1 vendor number vendor (2) bit 6 spindle current limit silim current has exceeded threshold (7) (8) bit 7 dead bit (unusable for timing reasons) n/a bit 8 emf xor output emfx changes state on xor of comparator a, b, c bit 9 emf a comparator output emfa positive high bit 10 dac write xor write (3) bit 11 transmission error tx_err * cselb occurs during active transmission (4) (7) bit 12 aux_write aux_wr toggles (5) bit 13 phase detect ph_det correct pwm phasing (6) bit 14 spindle forward sp_fwd * reports correct spindle rotation direction bit 15 note: the status register is readable during a por\ for in circuit testability. (1) overtemperature shutdown or warning do not cause por\. this arrangement allows graceful recovery from overtemperature cond itions. (2) vendor bit = 0 for unitrode, 1 for st. version number, bits 0,1 allow 4 chip versions. for the dolphin: bit 0 = 1, bit 1 = 0. this allows de- L6256 16/28
tection of the 12v combo vs. a dolphin chip (3) the dac write bit toggles every time a byte is written to the dac. this provides confirmation that the write actually took place. (4) detects spurious or missing sclk edge count between cselb edges. (5) flips state whenever either acr or vcr is written to successfully. this bit can be used together with the tx_err bit to see whether data was changed in the dolphin. (6) if the back emf chop blanking comparator goes high during the pwm on_del period, this bit is set to a one. see the back emf section. (7) bit is reset every time the register is accessed by the processor. (8) current limit bit works in run mode as well as in start mode. if current limit is ever detected in run mode, the chip shou ld be immediately tristated. (9) a1 in this bit indicates the correct (forward) phasing has been detected by the back emf circuitry. specifically, at the ne gative edge of sp_clk the back emf comparator must be in the expected state, or else the bit is cleared. updated on every negative sp_clk edge . spindle circuitry specifications spindle circuitry specifications symbol parameter test conditions min. typ. max. unit t brake braking time v emf = 7v 8 s (1) start mode current limit (bipolar) r ref = 62.5k 1% 1.6 a start mode current limit tolerance startup i peak 7% of programmed current (2) sr slew rate at speed (3) 12 15 v/ s vpwr current spiking at run speed 25% above spindle run current slew rate range adjustment 0.5:1 2:1 (4) run mode current limit 0.7 1.0 1.6 a spindle output current leakage (6) tristate -100 +100 a snubber caps 0 0.01 f 20% (1) braking on the spindle motor must remain active for the full braking time. this parameter is guaranteed by a leakage speci fication. full power brake is 3 seconds maximum. (2) excluding vcc tolerances. (3) slew rate at startup is limited by the parasitic diode revrse recovery timeso that the peak current spikes in the power sup ply are no larger than 25% above the motor run current. (4) slew circuitry must internally be able to drive stated snubber loads and be adjusted from 0.5 to 2 times the nominal value. this implies that rslew is able to be adjusted from 51k to 200k without causing circuit problems within the chip. (5) run mode current limit is strictly a protection mechanism to protect against spurious sp_clks or improperly programmed timi ng. max limit is a manifacturer limit determined by safe operating area considerations for the spindle fets. the minimum limit determi nes the maximum chip loading during run time. since this is strictly an internal limit, tolerances on this value are very wide. (6) spindle output leakage must not interfere with back emf sensing at any time. feedforward circuitry specifications symbol parameter test conditions min. typ. max. unit t off min(1) minimum off time 20/sr s pwm to dc conversion (2) 100 110 % of full scale chop frequency (3) 22 - khz psrr, spindle (4) 32 - - db (1)the purpose of toff min is to guarantee a full rise and fall time of the spindle chopper output circuitry at the minimum supply voltage. the timing circuit which determines toff min internally tracks the slew rate circuitry to keep this relationship true, while keeping toff min as small as possible. note: dynamic current limit considerations will usually limit the off time even further. (2) for the pwm to dc conversion, the following standard conditions apply: rpwm = 33k 5% input impedance of processor driver, 100 ohms assume driver is at 100% duty cycle rpwmdc = 100k 5% cdc = .0033 f 5% at these values, the output produces toff min at vpwr = 10 volts so that full scale is reachable. (3) with rslew = 100k 1%, cffc = 470 pf 5%, and including chip input capacitance, the output must not go below 20 khz over the range of toff min values. (4) psrr is defined as the ratio of average output voltage to the motor over the vpwr change: -20log10(dvout/dvpwr) it is tested by injecting a 0.6v peak square wave on vpwr and vdd from 1 hz to 10 khz. the specification applies over the enti re vpwr range. L6256 17/28
spindle logic interface specifications the digital interface to the controller chip has the following specifications: parameter min. max. units sp_clk, v oh v cc -0.8 v sp_clk, v ol 0.5 v emf_det v it+ 0.7 v cc v emf_det v it- 0.2vcc v emf_det hysteresis 0.1v cc 0.3v cc v emf_det i il -1 a emf_det i ih 1 a emf_det load 30pf, 1.6ma the sp_clk is a cmos output. the emf_det input is a schimitt trigger with the specified thresholds and leakage currents. vpwr blocking diode the blocking diode in the vpwr line is optionally a non-schottky part. if this occurs, schottkys should be used in the charge pump to provide the proper voltage at minimum supply. if regular diodes are used in both places, the part is functional (at 10% increased rdson in all drivers) at the lowered vpwr voltage. figure 9a. run mode spindle voltage waveforms figure 9b. start mode spindle voltage waveforms L6256 18/28
motor waveform specs. / diagrams it is necessary to center the center tap voltage by using symmetrical drive waveforms on the spindle motor drivers. this necessitates a chopped waveform on both the high and low side drivers. the pattern alternates between a high and low chop on every back emf cycle during run mode. note: the off time of the pwm chopping cycle is not disturbed when switching chop polarities for audible noise reasons. the change of polarity is produced by checking the emf state at the start of the on portion of the chop cycle. note: sp_clk positive pulse width ( tblank ) is 25 +/- 6% of the commutation period. supply voltage feedforward compensation the power supply voltage ripple arriving at the spindle power input pins would normally directly feed through into the spindle motor, causing un- acceptable speed deviations. the feedforward cir- cuitry cancels the voltage ripple on the power supply by correcting the pwm duty cycle appro- priately. it also reduces the pwm chop frequency to the minimum required to reduce noise and al- low slower slew rates. finally, it adds substantially to the resolution of the control loop by removing supply tolerances from the required range calcu- lations, and by cancelling power supply variations which would normally have to be taken into ac- count by the loop. supply feed forward circuitry the feedforward circuitry consists of: bias generator this circuitry generates a fixed current level that generates a very stable frequency in the local os- cillator that is independent of supply voltage. pwm_dc converter the processor pwm input has several problems which prevent it from being used directly. the pwm_dc converter converts the pwm input to a dc voltage so it can be rechopped. the bias generator provides a reference voltage that is used to convert the pwm_in\input from a voltage to a dc current value (set by rpwm, the input resistor). the duty cycle on this pin thus pro- duces a duty cycled current on the pwm_dc pin. the rc time constant and the valueof the resistor on the pwm_dc pin then converters this pulsed current into a dc voltage with a small amount of ripple. level shift the level shift takes the voltage on the pwm_dc pin and scales it to the resistor ladder reference (vrh) to set the ratio of dc voltage to reference voltage properly. local oscillator the local oscillator produces a sawtooth wave whose amplitude is directly proportional to the power supply voltage. it does this using the slew rate resistor (rslew) instead of the bandgap refer- ence, and cffc, the oscillator capacitor. the local oscillator must maintain a constant frequency so that it can be easily synchronized with the back emf detection circuitry. note the diode in the re- sistor ladder network, which compensates for the commutation state table bipolar bc/ state 0 (reset) ba/ state 1 ca/ state 2 cb/ state 3 ab/ state 4 ac/ state 5 note: before attempting tripolar operation, consult the application notes. tripolar abc high low high high low low high high low low high low low high high low low high L6256 19/28
output stage flyback diode voltage. off time one shot the off time one shot guarantees that a minimum off time occur in the output of the spindle pwm waveforms. this prevents subharmonic cycling, and prevents partial transition in the output wave- form. additionally, it provides a fixed time delay which allows acurate synchronizing of the pwm waveform with the commutation input (sp_clk). finally, it prevents tolerance buildups in the cir- cuitry because the pwm_dc circuitry can be de- signed to allow higher than full scale voltage with- out fear for causing audible subharmonics. output comparator this comparator produces the pwm chop duty cycle for use within the spindle drivers, now cor- rected for power supply variation. on delay comparator the on delay comparator provides a warning sig- nal for the back emf detection circuit brackets the worst part of the turnon transient that occurs on the back emf detection winding. figure 10. supply feedforward circuit diagrams. L6256 20/28
note: toff min is greater than the total fall and rise time of the spindle output waveforms. this ensures that a complete off cycle always occurs. ideally, toff and the slew rate would be related. tond is used by the back emf detection circuitry and is nominally about 20% of the total duty cy- cle. figure 11. supply feedforward support circuitry. figure 12. ramp oscillator waveforms. L6256 21/28
start mode during startup, all 3 back emf phases are used. the output going to the bemf_det line is the ex- clusive or of all 3 phases, and follows the polarity of whichever phase is currently tristated (relative to the center tap voltage). if the processor is driv- ing the motor directly from the cpr, the back emf circuitry is still active. tripolar mode by na- ture prevents emf detection. emf transitions are partially blanked by the controller chip in all modes. run phased mode the run phased mode is now the default (and only) state in the dolphin during run mode. the chop waveform is injected into the back emf waveform of the unused winding due to trans- former coupling and the action of the center tap. most of the transient is removed by using a high cmrr amplifier before the signal gets to the sample/hold circuit, and by holding during the off time of the chop. however, a small residual is left on the sample/hold waveform. this small tran- sient must be kept away from the back emf crossing point or it will cause an unstable loop. this can only be done if the pwm on edge is at the proper timing relative to the back emf point. a comparator is provided internally that generates the proper delay point by comparing the back emf waveform against a small offset voltage (settable externally). the programmer must then vary the commutation timing until the ph_det bit goes high, indicating that the chop and emf crossing waveforms are properly phased. this timing is produced by modifying the phase delay in the controller chip until ph_det is high. note that the ph_det bit is updated at the rising edge of the chop blanking comparator. if the on_del signal (the blanking signal that frames the emf on transient) is high during the edge, then the transient is in the proper position. the timing of the proper position is set by several external variables; the pwm frequency, the run- ning rpm speed, and the external reference volt- age. the relationships of the chop blanking compara- tor, the on_del signal, and the ph_det bit in the serial port are illustrated in fig. 13. back emf detection back emf detection has 2 different modes of operation: start mode (detemined by the manufacturer), and run phased mode. these are determined by the state of the start bit. back emf run mode specifications parameter test conditions min. typ. max. units rshold output impedance 25c 150 250 ? chop blank pulse width tchb (1) 23.5 25 27.5 s on delay width (2) 20 22 24 % of ramp rise time bemf start mode detect offset - vebias 40mv bemf detect hysteresis 10mv nominal (1) at 6000 rpm, 8 pole motor, sinusoidal emf from center tap to the a phase of 8 volts p-p, rref = 62.5k 1%, rref2 = 120k 1%. (2) on delay width is from the end of off time to the end of on_del. measured at max duty cycle (no off time due to feedforwar d compensa- tion). specification allows for toff min, to set nominally 20% width of total cycle time. figure 13. back emf chop blanking mode waveforms L6256 22/28
figure 14. back emf phase detection timing relantionships transitions transitioning from blind table drive to a back emf mode drive is handled in the following manner. re- member, data written to the cpr takes effect only when sp_clk receives a positive transition. the fol- lowing steps must be taken: the programmer must ensure that the last state before state 0 has been output to the cpr and clocked in using sp_clk. an all 1?s value is written to the cpr to enable the state counter. the next sp_clk will then produce a state 0 from the sequencer. voice coil driver (vcm) section vcm section specifications parameter test conditions min. typ. max. units large signal voltage gain output swing from 1 to 10v 70 db gain bandwidth product, a-amp 4.5 mhz 3db bw, total loop 25 khz phase margin, a amp 45 slew rate, a amp 1.4 2 v/ s gain, b amp -1.17 *a gain 3db bandwidth, b 2.3 mhz total a+b saturation resistance i = 600ma 2 3 ? offset reflected to i sense d/a reg @ 0 30 mv (1) vpwr/2 input impedance 25c 38 50 65 k ? loopback output threshold (2) 25c 50 ma/ ? v sst saturated seek comparator threshold output saturated either polarity 30 50 70 mv (1) total current offset of vcm loop must not exceed 3% of full scale current. (2) optional. L6256 23/28
current sense amplifier specifications parameter test conditions min. typ. max. units current amp gain over temp 2.35 2.4 2.45 v/v available output current 600 a current amp cmrr including inductive flyback range, to 25khz 60 db (1) (1) charge buildup on current amp input must not occur. dac section specification general parameters parameter test conditions min. typ. max. units differential non linearity 1lsb integral non lineraity best fit 2 lsb psrr 10 - 14v 60 db settle time 90% 0.5 1.2 s output voltage span vmin to vmax 2.5 v voltage span tolerance -7 +7 % output amp impedance full temp 5 ? output short cct current output shorted 1 ma coding 2?s complement park section specifications parameter test conditions min. typ. max. units park voltage 0.45 0.5 0.55 v 3.3v voltage regulator voltage regulator specifications current sense comparator parameter test conditions min. typ. max. units dc output voltage t j = 0 to 160c 3.135 +3.465 v ac transient 1ma to full load 3% of dc out. volt. (3) vilimit (1) t j = 0 to 160c 0.24 0.3 0.36 v foldback current limit ratio (2) output shorted to ground 3:1 ratio (1) vilimit is the voltage at which current limit begins to occur, as seen across rcl (see block diagram) as measured by the uv detection oc- curing. (2) foldback current limit prevents excessive power dissipation in the pass element under short circuit conditions. the ratio i s the current flowing at current limit when the pass element under short circuit conditions. the ratio is the current flowing at current limi t when the pass element is delivering full voltage (when uv first occurs), over the current in the pass element when the output is shorted to g round. (3) dc and ac transient requirements may be mixed, as long as the total deviation from 3.3v does not exceed dvreg as specified under the critical specifications in section 6 of this specification. driver output parameter test conditions min. typ. max. units output current v o < 3.5v 0.5 ma output high voltage i = -0.1ma, v = 5v vdd-2 v output impedance 25c 50 ? L6256 24/28
operational description at power up, the regulator saturates the pass ele- ment until 3.3v is reached. if the 5v supply rises quickly, the regulator will current limit until 3.3v is reached. the initial current limit level is about 1/3 of the full voltage current limit level, to limit power dissipation in the pass element. once the 3.3v regulation level is reached, the regulator mantains thi svoltage regardless of load changes, even if the dolphin goes into thermal limit. current limit provides a signal which also causes uv and a por to occur. if the 5v input is shut down before the 12v supply is removed, the pass element will drag down the 3.3v due to the internal diode. this prevents back biasing effects from occuring in the chips pow- ered by the regulator. rgate (see block diagram) is provided to desensi- tize the pass element to layout problems. in most applications it will not be needed. charge pump charge pump specification parameter conditions min. typ. max. unit slew rate run mode 600 v/ s rms current all conditions 400 ma peak current all conditions 600 ma application notes and requirements serial port general format requirements 1. serial port packets must be sent without inter- vening data. the dead space between data bytes and after write packets addressed to this chip must be observed. 2. read: a turnaround delay of 1 cycle minimum is expected on a read packet, between the ad- dress byte (written) and the first data byte read back. this is necessary only for data ad- dressed directly to the combo, and is normally satisfied by the processor port turnaround re- quirements. 3. write: both bytes must be written to the serial port in rapid succession, disabling interrupts during the write period. 4. if the dead cycle between write packets to the dolphin is not observed, an error will also occur. this is important at high data rates. (see manufacturer data specs). 5. read: same as 4. thermal shutdown the serial port becomes inoperative during ther- mal shutdown. all data coming back is high. if the chip receives data words in which all bits are high, the chip is non-functional. this is invisible to the processor when compared with the thermal time constants and the detector hysteresis built into the chip. bit 3 of all registers is dedicated to thermal shut- down detection. if it is faster to check just a sin- gle bit rather than using a full compare, bit 3 is available in every read register. note: this was necessary in order to guarantee that all ff?s would truly represent only a thermal shutdown situation. vcm driver software must set the vcm gain to 12:1 before enabling the vcm coil after spinup. a transient will occur while the amplifier slews up to its bias point. allow a transient settle time of several mi- croseconds before the vcm driver has settled to its fully enabled state. spindle driver brake/park the register bits have been carefully arranged to allow the vcm software driver to run by looking only at the vcm control register. a register brake would normally be initiated by the spindle driver routine, by setting the register brake bit in the aux control register. the dolphin will then raise the park delay bit in the vcm control register, which the vcm driver can then use to indicate that a park has commenced. thus, there is no need for the drivers to be directly linked through software flags. the register brake bit function has been changed to allow intermittent duty cycling during start mode, to supply additional damping. there are some restrictions on its use. back emf detection - initialization the back emf detection in start differs from that in run. when transitioning from start to run, the first detected phase will always be the a negative crossing. L6256 25/28
resync algorithm the firmware must use start mode to resync the back emf signal when attempting to resynchron- ize the spindle speed. please consult the motion control group for more details. the spinup algo- rithm is available as a separate specification. design formulas spindle startup current spindle startup current is set up using the follow- ing formula: imax = rref ? 1.6 62.5k in amps the vcc tolerances are added to the final design value. back emf window width window width is calculated for other than the nominal conditions by ratioing the window voltage against the current nominal design point: tw = 25 ? rref rref + rref ? 62.5 + 120 62.5 ? 8v vemf ? 6000 rpm where: vemf is the nominal expected back emf to peak voltage, rpm is the target rpm of the drive; tw is the resultatnt window width. if the window is too small or too large, transients will affect the detection. chopping waveform there is a requirement on the back emf wave- form. the chopping transients must die out be- fore the waveform is sampled or speed errors will result. this puts limits on the damping resistors if pre- sent, which depend on motor inductance, eddy current losses and the like. sh_out components the sh_out components must be designed so that the rate of droop of the capacitor matches the back emf waveform at its negative going zero crossing point when the drive is on speed. components for one part will work for the other part, but voltage waveforms are scaled differently between the two parts. the sh_out resistor should be as large as possi- ble. this minimizes the internal impedances and sample/hold errors. 100k is the nominal design point. additional design formuals are included in the applications notes for each vendor?s parts and in western digital?s internal application notes. L6256 26/28
plcc44 package mechanical data dim. mm inch min. typ. max. min. typ. max. a 17.4 17.65 0.685 0.695 b 16.51 16.65 0.650 0.656 c 3.65 3.7 0.144 0.146 d 4.2 4.57 0.165 0.180 d1 2.59 2.74 0.102 0.108 d2 0.68 0.027 e 14.99 16 0.590 0.630 e 1.27 0.050 e3 12.7 0.500 e4 1.98 0.078 f 0.46 0.018 f1 0.71 0.028 g 0.101 0.004 m 1.16 0.046 m1 1.14 0.045 L6256 27/28
information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specification mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously s upplied. sgs- thomson microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of sgs-thomson microelectronics. ? 1997 sgs-thomson microelectronics ? printed in italy ? all rights reserved sgs-thomson microelectronics group of companies australia - brazil - canada - china - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco - the n etherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. L6256 28/28

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